Igo8 navigation software windows ce. C: iverilog samples verilog_operators2.v.html module tb_opereators ( ); reg [ 1: 0 ] r1; reg [ 1: 0 ] r2; reg [ 1: 0 ] acc; initial begin $display ( '****************************' ); $monitor ( ' Time=%t n ACC =%b', $time, acc ); r1 = 2'b10; r2 = 2'b11; /* universal NAND opeartion */ acc = r1 ~& r2; $display ( '******* Universal Bitwise NAND ***********' ); /* NOR */ # 5 acc = r1 ~  r2; $display ( '******* Universal Bitwise NOR ************' ); # 15 r1 = 2'b00; r2 = 2'b01; /* Bitwise XNOR */ # 5 acc = r1 ~^ r2; $display ( '****** Universal Bitwise XNOR **********' ); $finish; end endmodule.

Jan 26, 2013  Posted by kishorechurchil in verilog code for Accumulator and testbench Tagged: Accumulator, testbench, Verilog Code, verilog code for Accumulator and testbench Post navigation.